1. Field of the Invention
The present invention relates to a flip chip semiconductor device having a semiconductor chip packaged therein.
2. Description of the Background Art
FIG. 6 is a cross-sectional view of a conventional flip chip semiconductor device having a semiconductor chip packaged therein. As shown in FIG. 6, a plurality of protruding electrode portions 20 each including a bump electrode 2 and a land electrode 3 are formed on the lower surface of an LSI chip 1. The bump electrodes 2 are electrically connected to electrodes of the LSI chip 1 although not shown in FIG. 6.
The LSI chip 1, the plurality of bump electrodes 2 and the plurality of land electrodes 3 are sealed in a resin 4. The land electrodes 3 are exposed at the lower interface of the resin 4. The plurality of land electrodes 3 and a plurality of connecting terminals 5 are directly connected respectively to each other by melting through the application of heat. In this manner, a signal from the electrodes of the LSI chip 1 may be provided through the connecting terminals 5. The connecting terminals 5 are terminals for connection to a mounting substrate. The structure of FIG. 6 is disclosed in, for example, Japanese Patent Application Laid-Open No. 6-302604 (1994).
As illustrated in FIG. 6, the flip chip semiconductor device including the LSI chip 1 packaged therein has a high packaging density to achieve size reduction and high functions at low costs.
In specific applications, for example, when a semiconductor device packaged by a conventional manner such as wire bonding is replaced with the flip chip semiconductor device connecting terminals of the mounting substrate are not packaged at a high density in the majority of cases.
In such a case, it is impossible to use the flip chip semiconductor device since the connecting terminals of the semiconductor device packaged at a high density by the flip chip technique are not compatible with the connecting terminals of the mounting substrate packaged at a low density.
Additionally, the thermal stress caused by the difference in thermal expansion coefficient between the LSI chip 1 and the mounting substrate exerts adverse effects on electrically connecting means (the bump electrodes 2, the land electrodes 3 and the connecting terminals 5) formed between the LSI chip 1 and the mounting substrate, resulting in a shortened life due to fatique.